|
#define | VL53L0X_REG_SYSRANGE_START 0x00 |
|
#define | VL53L0X_REG_SYSTEM_SEQUENCE_CONFIG 0x01 |
|
#define | VL53L0X_REG_SYSTEM_INTERMEASUREMENT_PERIOD 0x04 |
|
#define | VL53L0X_REG_SYSTEM_RANGE_CONFIG 0x09 |
|
#define | VL53L0X_REG_SYSTEM_INTERRUPT_CONFIG_GPIO 0x0A |
|
#define | VL53L0X_REG_SYSTEM_INTERRUPT_CLEAR 0x0B |
|
#define | VL53L0X_REG_SYSTEM_THRESH_HIGH 0x0C |
|
#define | VL53L0X_REG_SYSTEM_THRESH_LOW 0x0E |
|
#define | VL53L0X_REG_RESULT_INTERRUPT_STATUS 0x13 |
|
#define | VL53L0X_REG_RESULT_RANGE_STATUS 0x14 |
|
#define | VL53L0X_REG_CROSSTALK_COMPENSATION_PEAK_RATE_MCPS 0x20 |
|
#define | VL53L0X_REG_PRE_RANGE_CONFIG_MIN_SNR 0x27 |
|
#define | VL53L0X_REG_ALGO_PART_TO_PART_RANGE_OFFSET_MM 0x28 |
|
#define | VL53L0X_REG_ALGO_PHASECAL_LIM 0x30 |
|
#define | VL53L0X_REG_ALGO_PHASECAL_CONFIG_TIMEOUT 0x30 |
|
#define | VL53L0X_REG_GLOBAL_CONFIG_VCSEL_WIDTH 0x32 |
|
#define | VL53L0X_REG_HISTOGRAM_CONFIG_INITIAL_PHASE_SELECT 0x33 |
|
#define | VL53L0X_REG_FINAL_RANGE_CONFIG_MIN_COUNT_RATE_RTN_LIMIT 0x44 |
|
#define | VL53L0X_REG_FINAL_RANGE_CONFIG_VALID_PHASE_LOW 0x47 |
|
#define | VL53L0X_REG_FINAL_RANGE_CONFIG_VALID_PHASE_HIGH 0x48 |
|
#define | VL53L0X_REG_DYNAMIC_SPAD_NUM_REQUESTED_REF_SPAD 0x4E |
|
#define | VL53L0X_REG_DYNAMIC_SPAD_REF_EN_START_OFFSET 0x4F |
|
#define | VL53L0X_REG_PRE_RANGE_CONFIG_VCSEL_PERIOD 0x50 |
|
#define | VL53L0X_REG_PRE_RANGE_CONFIG_TIMEOUT_MACROP_HI 0x51 |
|
#define | VL53L0X_REG_PRE_RANGE_CONFIG_TIMEOUT_MACROP_LO 0x52 |
|
#define | VL53L0X_REG_HISTOGRAM_CONFIG_READOUT_CTRL 0x55 |
|
#define | VL53L0X_REG_PRE_RANGE_CONFIG_VALID_PHASE_LOW 0x56 |
|
#define | VL53L0X_REG_PRE_RANGE_CONFIG_VALID_PHASE_HIGH 0x57 |
|
#define | VL53L0X_REG_MSRC_CONFIG_CONTROL 0x60 |
|
#define | VL53L0X_REG_PRE_RANGE_CONFIG_SIGMA_THRESH_HI 0x61 |
|
#define | VL53L0X_REG_PRE_RANGE_CONFIG_SIGMA_THRESH_LO 0x62 |
|
#define | VL53L0X_REG_PRE_RANGE_MIN_COUNT_RATE_RTN_LIMIT 0x64 |
|
#define | VL53L0X_REG_FINAL_RANGE_CONFIG_MIN_SNR 0x67 |
|
#define | VL53L0X_REG_FINAL_RANGE_CONFIG_VCSEL_PERIOD 0x70 |
|
#define | VL53L0X_REG_FINAL_RANGE_CONFIG_TIMEOUT_MACROP_HI 0x71 |
|
#define | VL53L0X_REG_FINAL_RANGE_CONFIG_TIMEOUT_MACROP_LO 0x72 |
|
#define | VL53L0X_REG_POWER_MANAGEMENT_GO1_POWER_FORCE 0x80 |
|
#define | VL53L0X_REG_SYSTEM_HISTOGRAM_BIN 0x81 |
|
#define | VL53L0X_REG_GPIO_HV_MUX_ACTIVE_HIGH 0x84 |
|
#define | VL53L0X_REG_VHV_CONFIG_PAD_SCL_SDA__EXTSUP_HV 0x89 |
|
#define | VL53L0X_REG_I2C_SLAVE_DEVICE_ADDRESS 0x8A |
|
#define | VL53L0X_REG_GLOBAL_CONFIG_SPAD_ENABLES_REF_0 0xB0 |
|
#define | VL53L0X_REG_GLOBAL_CONFIG_SPAD_ENABLES_REF_1 0xB1 |
|
#define | VL53L0X_REG_GLOBAL_CONFIG_SPAD_ENABLES_REF_2 0xB2 |
|
#define | VL53L0X_REG_GLOBAL_CONFIG_SPAD_ENABLES_REF_3 0xB3 |
|
#define | VL53L0X_REG_GLOBAL_CONFIG_SPAD_ENABLES_REF_4 0xB4 |
|
#define | VL53L0X_REG_GLOBAL_CONFIG_SPAD_ENABLES_REF_5 0xB5 |
|
#define | VL53L0X_REG_GLOBAL_CONFIG_REF_EN_START_SELECT 0xB6 |
|
#define | VL53L0X_REG_RESULT_PEAK_SIGNAL_RATE_REF 0xB6 |
|
#define | VL53L0X_REG_RESULT_CORE_AMBIENT_WINDOW_EVENTS_RTN 0xBC |
|
#define | VL53L0X_REG_SOFT_RESET_GO2_SOFT_RESET_N 0xBF |
|
#define | VL53L0X_REG_RESULT_CORE_RANGING_TOTAL_EVENTS_RTN 0xC0 |
|
#define | VL53L0X_REG_IDENTIFICATION_MODEL_ID 0xC0 |
|
#define | VL53L0X_REG_IDENTIFICATION_REVISION_ID 0xC2 |
|
#define | VL53L0X_REG_RESULT_CORE_AMBIENT_WINDOW_EVENTS_REF 0xD0 |
|
#define | VL53L0X_REG_RESULT_CORE_RANGING_TOTAL_EVENTS_REF 0xD4 |
|
#define | VL53L0X_REG_OSC_CALIBRATE_VAL 0xF8 |
|