ChibiOS  21.6.0
hal_mii.h
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1 /*
2  ChibiOS - Copyright (C) 2006..2018 Giovanni Di Sirio
3 
4  Licensed under the Apache License, Version 2.0 (the "License");
5  you may not use this file except in compliance with the License.
6  You may obtain a copy of the License at
7 
8  http://www.apache.org/licenses/LICENSE-2.0
9 
10  Unless required by applicable law or agreed to in writing, software
11  distributed under the License is distributed on an "AS IS" BASIS,
12  WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
13  See the License for the specific language governing permissions and
14  limitations under the License.
15 */
16 
17 /**
18  * @file hal_mii.h
19  * @brief MII macros and structures.
20  *
21  * @addtogroup MII
22  * @{
23  */
24 
25 #ifndef MII_H
26 #define MII_H
27 
28 /**
29  * @name Generic MII registers
30  * @{
31  */
32 #define MII_BMCR 0x00 /**< Basic mode control register. */
33 #define MII_BMSR 0x01 /**< Basic mode status register. */
34 #define MII_PHYSID1 0x02 /**< PHYS ID 1. */
35 #define MII_PHYSID2 0x03 /**< PHYS ID 2. */
36 #define MII_ADVERTISE 0x04 /**< Advertisement control reg. */
37 #define MII_LPA 0x05 /**< Link partner ability reg. */
38 #define MII_EXPANSION 0x06 /**< Expansion register. */
39 #define MII_ANNPTR 0x07 /**< 1000BASE-T control. */
40 #define MII_CTRL1000 0x09 /**< 1000BASE-T control. */
41 #define MII_STAT1000 0x0a /**< 1000BASE-T status. */
42 #define MII_ESTATUS 0x0f /**< Extended Status. */
43 #define MII_PHYSTS 0x10 /**< PHY Status register. */
44 #define MII_MICR 0x11 /**< MII Interrupt ctrl register. */
45 #define MII_DCOUNTER 0x12 /**< Disconnect counter. */
46 #define MII_FCSCOUNTER 0x13 /**< False carrier counter. */
47 #define MII_NWAYTEST 0x14 /**< N-way auto-neg test reg. */
48 #define MII_RERRCOUNTER 0x15 /**< Receive error counter. */
49 #define MII_SREVISION 0x16 /**< Silicon revision. */
50 #define MII_RESV1 0x17 /**< Reserved. */
51 #define MII_LBRERROR 0x18 /**< Lpback, rx, bypass error. */
52 #define MII_PHYADDR 0x19 /**< PHY address. */
53 #define MII_RESV2 0x1a /**< Reserved. */
54 #define MII_TPISTATUS 0x1b /**< TPI status for 10Mbps. */
55 #define MII_NCONFIG 0x1c /**< Network interface config. */
56 /** @} */
57 
58 /**
59  * @name Basic mode control register
60  * @{
61  */
62 #define BMCR_RESV 0x007f /**< Unused. */
63 #define BMCR_CTST 0x0080 /**< Collision test. */
64 #define BMCR_FULLDPLX 0x0100 /**< Full duplex. */
65 #define BMCR_ANRESTART 0x0200 /**< Auto negotiation restart. */
66 #define BMCR_ISOLATE 0x0400 /**< Disconnect DP83840 from MII. */
67 #define BMCR_PDOWN 0x0800 /**< Powerdown. */
68 #define BMCR_ANENABLE 0x1000 /**< Enable auto negotiation. */
69 #define BMCR_SPEED100 0x2000 /**< Select 100Mbps. */
70 #define BMCR_LOOPBACK 0x4000 /**< TXD loopback bit. */
71 #define BMCR_RESET 0x8000 /**< Reset. */
72 /** @} */
73 
74 /**
75  * @name Basic mode status register
76  * @{
77  */
78 #define BMSR_ERCAP 0x0001 /**< Ext-reg capability. */
79 #define BMSR_JCD 0x0002 /**< Jabber detected. */
80 #define BMSR_LSTATUS 0x0004 /**< Link status. */
81 #define BMSR_ANEGCAPABLE 0x0008 /**< Able to do auto-negotiation. */
82 #define BMSR_RFAULT 0x0010 /**< Remote fault detected. */
83 #define BMSR_ANEGCOMPLETE 0x0020 /**< Auto-negotiation complete. */
84 #define BMSR_MFPRESUPPCAP 0x0040 /**< Able to suppress preamble. */
85 #define BMSR_RESV 0x0780 /**< Unused. */
86 #define BMSR_10HALF 0x0800 /**< Can do 10mbps, half-duplex. */
87 #define BMSR_10FULL 0x1000 /**< Can do 10mbps, full-duplex. */
88 #define BMSR_100HALF 0x2000 /**< Can do 100mbps, half-duplex. */
89 #define BMSR_100FULL 0x4000 /**< Can do 100mbps, full-duplex. */
90 #define BMSR_100BASE4 0x8000 /**< Can do 100mbps, 4k packets. */
91 /** @} */
92 
93 /**
94  * @name Advertisement control register
95  * @{
96  */
97 #define ADVERTISE_SLCT 0x001f /**< Selector bits. */
98 #define ADVERTISE_CSMA 0x0001 /**< Only selector supported. */
99 #define ADVERTISE_10HALF 0x0020 /**< Try for 10mbps half-duplex. */
100 #define ADVERTISE_10FULL 0x0040 /**< Try for 10mbps full-duplex. */
101 #define ADVERTISE_100HALF 0x0080 /**< Try for 100mbps half-duplex. */
102 #define ADVERTISE_100FULL 0x0100 /**< Try for 100mbps full-duplex. */
103 #define ADVERTISE_100BASE4 0x0200 /**< Try for 100mbps 4k packets. */
104 #define ADVERTISE_PAUSE_CAP 0x0400 /**< Try for pause. */
105 #define ADVERTISE_PAUSE_ASYM 0x0800 /**< Try for asymetric pause. */
106 #define ADVERTISE_RESV 0x1000 /**< Unused. */
107 #define ADVERTISE_RFAULT 0x2000 /**< Say we can detect faults. */
108 #define ADVERTISE_LPACK 0x4000 /**< Ack link partners response. */
109 #define ADVERTISE_NPAGE 0x8000 /**< Next page bit. */
110 
111 #define ADVERTISE_FULL (ADVERTISE_100FULL | ADVERTISE_10FULL | \
112  ADVERTISE_CSMA)
113 #define ADVERTISE_ALL (ADVERTISE_10HALF | ADVERTISE_10FULL | \
114  ADVERTISE_100HALF | ADVERTISE_100FULL)
115 /** @} */
116 
117 /**
118  * @name Link partner ability register
119  * @{
120  */
121 #define LPA_SLCT 0x001f /**< Same as advertise selector. */
122 #define LPA_10HALF 0x0020 /**< Can do 10mbps half-duplex. */
123 #define LPA_10FULL 0x0040 /**< Can do 10mbps full-duplex. */
124 #define LPA_100HALF 0x0080 /**< Can do 100mbps half-duplex. */
125 #define LPA_100FULL 0x0100 /**< Can do 100mbps full-duplex. */
126 #define LPA_100BASE4 0x0200 /**< Can do 100mbps 4k packets. */
127 #define LPA_PAUSE_CAP 0x0400 /**< Can pause. */
128 #define LPA_PAUSE_ASYM 0x0800 /**< Can pause asymetrically. */
129 #define LPA_RESV 0x1000 /**< Unused. */
130 #define LPA_RFAULT 0x2000 /**< Link partner faulted. */
131 #define LPA_LPACK 0x4000 /**< Link partner acked us. */
132 #define LPA_NPAGE 0x8000 /**< Next page bit. */
133 
134 #define LPA_DUPLEX (LPA_10FULL | LPA_100FULL)
135 #define LPA_100 (LPA_100FULL | LPA_100HALF | LPA_100BASE4)
136 /** @} */
137 
138 /**
139  * @name Expansion register for auto-negotiation
140  * @{
141  */
142 #define EXPANSION_NWAY 0x0001 /**< Can do N-way auto-nego. */
143 #define EXPANSION_LCWP 0x0002 /**< Got new RX page code word. */
144 #define EXPANSION_ENABLENPAGE 0x0004 /**< This enables npage words. */
145 #define EXPANSION_NPCAPABLE 0x0008 /**< Link partner supports npage. */
146 #define EXPANSION_MFAULTS 0x0010 /**< Multiple faults detected. */
147 #define EXPANSION_RESV 0xffe0 /**< Unused. */
148 /** @} */
149 
150 /**
151  * @name N-way test register
152  * @{
153  */
154 #define NWAYTEST_RESV1 0x00ff /**< Unused. */
155 #define NWAYTEST_LOOPBACK 0x0100 /**< Enable loopback for N-way. */
156 #define NWAYTEST_RESV2 0xfe00 /**< Unused. */
157 /** @} */
158 
159 /**
160  * @name PHY identifiers
161  * @{
162  */
163 #define MII_DM9161_ID 0x0181b8a0
164 #define MII_AM79C875_ID 0x00225540
165 #define MII_KSZ8081_ID 0x00221560
166 #define MII_KS8721_ID 0x00221610
167 #define MII_STE101P_ID 0x00061C50
168 #define MII_DP83848I_ID 0x20005C90
169 #define MII_LAN8710A_ID 0x0007C0F1
170 #define MII_LAN8720_ID 0x0007C0F0
171 #define MII_LAN8742A_ID 0x0007C130
172 #define MII_LAN8740A_ID 0x0007C110
173 /** @} */
174 
175 #endif /* MII_H */
176 
177 /** @} */